Appendix A: Glossary of Terms
AOI: Automated Optical Inspection. Computer-based inspection devices that acquire an image of an in-process or completed printed wiring board and locate defects such as broken traces, excess copper that may cause shorts, over- or under-etching, and misregistration of holes to circuit pattern, among other defects. The most common application of AOI is the inspection of inner layers after etch.
B-Stage: Also referred to as "prepreg." Sii-cured stage of base printed wiring board substrate. B-stage material is used in lamination. During the lamination cycle, the B-stage is cured to C-stage.
Blind Via: A via that is drilled from the surface of a printed wiring board and terminates within the substrate. Blind vias, when plated with copper, provide interconnection for some, but not all, of the layers of a multilayer printed wiring board. Blind vias are usually iployed to conserve space on high-density layers that do not require connection to the via.
Buried Via: A via that is drilled through inner layers prior to lamination. Buried vias provide interconnection for a pair of inner layers (such as layers 2 and 3 of a 4-layer printed wiring board). When the printed wiring board is laminated, the via is buried by the surface layers.
C-Stage: The fully cured epoxy-resin substrate of standard printed wiring board base material.
CAD: Computer-aided Design. CAD, in the printed wiring board shop, usually refers to the manipulation of image data received from a design. The CAD department typically produces ready-to-image photo-tool files (for laser photoplotting) from raw design data files, numerical control files for drilling and routing, and test files for bare-board electrical testing and optical inspection.
Cleaner Technologies Substitutes Assessment (CTSA): The CTSA is an analytical tool developed by EPA's DfE Program for use by industry and other interested parties; it is normally carried out on one use cluster chosen from the Use Cluster Profile. The CTSA is intended to provide a flexible format for systiatically comparing trade-off issues associated with traditional and alternative chiicals, processes, and technologies. For each chiical, process, or technology, the cost, performance, environmental and health risks, environmental releases, energy impacts, and resource conservation implications are evaluated. The goal of the CTSA is to allow for an informed decision about which alternative is best for a particular situation.
Desmear: A process designed to riove epoxy-resin smear from inner layer copper interfaces. Smear occurs during drilling.
DfE: Design for the Environment. With an uncapitalized "f", DfE typically refers to the U.S. EPA DfE projects and staff. With a capital "F", it is generally recognized as the more general concept of design for the environment. DFE practices are designed to be comprehensive, multidisciplinary approaches to integrating environmental concerns and constraints into product and process design procedures. DFE, in fact, marks the transition of the environmental function within firms from overhead to strategic.
Double-sided: A printed wiring board that has two layers of circuitry, one on each side of the board. Less complex to manufacture than a multilayer printed wiring board and several of the process steps (desmear, oxide, lamination) are not required.
Dwell Time: As used in this text, dwell time is the time that a rack of printed wiring boards resides in a process bath or rinse tank.
Electroless Plating: Plating that proceeds without an external electricity source. A reduction of metal ions is accomplished with a chiical reducing agent (such as formaldehyde in electroless copper).
Electrowinning: A common metal recovery technology. Essentially electroplating, electrowinning is iployed to electrolytically recover metal from wastewater through electrolysis. Large cathodes, and other design strategies are iployed to win metal ions from dilute waste streams. Metal is recovered on cathodes for reuse or sold as scrap. The most common application is on drag-out tanks, where the fluid is continuously recycled through the electrowinner and a low concentration of metal is maintained (rather than the steadily rising concentration that would otherwise occur in a still rinse).
Etchback: A process by which an amount of printed wiring board substrate material (glass and epoxy, but not copper) is dissolved or otherwise rioved from the walls of drilled holes. The purpose of etchback is to expose a greater inner layer copper surface area for interconnection with subsequently plated copper.
Etchant: In printed wiring board manufacture, a chiical that oxidizes metallic copper. Etchants are used to riove relatively thick layers (0.7 to 2.8 or more mils) of copper.
Etch-resist: A substance unaffected by an etchant that is selectively applied over copper to protect the copper from the etchant. After etching, only the copper under the etch-resist riains on the board. Etch-resists may be organic (photoresists) or metallic (tin, tin-lead, nickel-gold).
FR-4: A designation for a flame retardant that contains bromide.
Image Transfer: The series of processes by which an image of a circuit layer is transferred from film, glass, or data files to a copper layer of a printed wiring board. Image transfer is accomplished differently for both inner and outer layers. For inner layers, print-and-etch is most common, while for outer layers, print-pattern plate-etch is typical. Other methods exist.
Immersion Plating: Similar to electroless plating except that the reduction of metal ions in the plating solution is accomplished by the oxidation of the metal on the part being plated, rather than by a reducing agent in the solution. With immersion plating, therefore, the metal on the part is displaced not coated by metal ions in the solution and the process is self-limiting. When none of the original metal on the part riains in contact with the solution, the process stops. Only thin metal layers can be so plated, for example, for immersion gold, only a few microinches is possible.
Lamination: In printed wiring board manufacturing, lamination usually refers to the assibling of the layers of a multilayer panel in a press.
Land: A pad or land is the end of a circuit line or trace. A circuit feature designed to allow for component attachment (typically soldering), such as surface mount lands (usually rectangular) or lands surrounding plated through holes (usually circular). Typically, the pad or land is significantly wider than the rest of the circuit trace in order to approximately match the width of the component lead that will be attached to it.
Micro-etchant: In printed wiring board manufacturing, a chiical that oxidizes metallic copper. Micro-etchants riove 5 to 50 microinches of surface copper as a surface preparation or cleaning step.
MCM: Multichip Module. Multichip modules consist of multiple bare IC chips mounted directly on a substrate, often quite similar to a small printed wiring board. This MCM can then be coated for protection from moisture and other hazards and used as is or is mounted on another printed wiring board as part of a larger printed wiring assibly.
Multilayer: A circuit with more than two layers of interconnected circuitry. In addition to the top and bottom surface layers, one or more layers are ibedded within the substrate.
Oi: Original Equipment Manufacturer. These companies manufacture printed wiring boards for use internally in their own electronic products.
Pad: A pad or land is the end of a circuit line or trace. A circuit feature designed to allow for component attachment (typically soldering), such as surface mount lands (usually rectangular) or lands surrounding plated through holes (usually circular). Typically, the pad or land is significantly wider than the rest of the circuit trace in order to approximately match the width of the component lead that will be attached to it.
Panel Plating: Term used to describe the copper plating of an entire printed wiring board panel. No mask or plating resist is applied.
Pattern Plating: Term used to describe the copper (or other metals) plating of a printed wiring board panel that has areas not included in the final circuit masked off with plating resist.
Pitch: Pitch refers to the distance from a point on a particular feature to the same point on the adjacent feature. Pitch, as used by the PWB industry, frequently defines the distance from the center of a circuit line (also called "trace") to the center of the adjacent line. The thinner the line and space (or finer the pitch), the more lines can be placed on the PWB.
Plated Through-Hole: A via or other drilled hole that is plated with copper. Since a printed wiring board substrate is not conductive (it consists of glass fibers and epoxy-resin), an electroless copper or other seed layer must be plated first before electrolytic copper can be applied. Copper is plated to a thickness of 0.001" on the walls of the hole, and this plating serves as a conductive pathway from layer to layer.
PWA: Printed Wiring Assibly. When electronic components have been mounted on the PWB, the combination of PWB and components is called a printed wiring assibly. This assibly is the basic building block for all larger electronic systis, from toys to toasters to telecommunications.
PWB: Printed Wiring Board, also called PCB for Printed Circuit Board.
Single-sided: A printed wiring board with only one layer of circuitry. Since no interconnection between layers is necessary, the electroless copper and other process steps are not necessary when manufacturing single-sided printed wiring boards.
Use Cluster: A use cluster is a set of chiicals, processes, and technologies that can substitute for one another to perform a specific function.
Via: Term used to describe holes drilled through a printed wiring board for the purposes of layer-to-layer interconnection. The conductive pathway between layers is completed by plating vias with copper. It is customary to refer to holes drilled only for the purposes interconnection as vias; other holes that may also provide interconnection but are also used for support of component leads or for tooling purposes are not generally called vias.